Design Technology for Digital Circuit Testware

 

It is discussed the two-pass digital circuit testware design technology which unites DFT and ATPG and provides automatic generation of the recommendations on circuit modifications to meet HiFi test design. The practice of CAD applications is discussed too.

 

Computer-aided design (CAD) of digital circuits, for example MAX Plus II of „Altera” firm (USA), see www.altera.com, are usually supplied with the graphic circuit editor, technical design and simulation means. Sometimes CADs are supplied with the means of the fault coverage analysis (they are absent in MAX Plus II). Only few CADs have Automatic Test Pattern Generation (ATPG) facility, see e.g. www.acugen.com. Problem faced ATPG causes that CADs are supplied with the Design for Test (DFT) tools. Circuit is checked to meet certain design rules in DFT process traditionally. Controllability and observability measures are sometimes calculated, but there is no fault coverage prediction. Is it possible that used test generator is capable to create the HiFi test for the circuit? DFT tools show problems usually but does not specify ways of their overcoming.

A regular test synthesis method [1] was developed by „Testward Lab“. ATPG system was used for many years in industry [2]. Now considering ATPG and DFT subsystems together in the Tw-CAD (Testware CAD), let’s introduce the term „testware“, meaning union of all HiFi test design components. The offered testability measure allows estimating of the initial circuit. Calculated measure is compared with that of the ATPG ability predicting the test quality on this base. Modifications to improve testability are been produced automatically too if they needed. In the Tw-CAD the testware is been produced by transparent technology:

·       designer makes order of  desirable quality test

·       the Tw-CAD predicts expected test quality and recommends some modifications to reach the desirable quality level

·       designer looks for balance between desirable test quality and offered modifications of the circuit and than realizes modifications

·       the HiFi test is generated for the modified circuit

        

Circuit analysis and circuit classification

The purpose is to use considered controllability and observability measures of nodes [3] to estimate testability measure and to classify circuits. Testability is ability to design the HiFi test automatically. Let bit is the logic value „0” or „1” that assigned to an input, FF node, combinational or buffer node or circuit output. Bits are ranged by controllability, observability and testability measures when creating of circuit model.

Controllability measure of bit defines, how is it difficult to control bit on the input side:

·       the greater measure - the worse controllability

·       the best measures (=1) are assigned to input bits

·       the measure of other bits shows how many bits should been toggled on average before estimated bit toggled

·       if bit is not toggled, its measure is equal 0, and it refers to as belonged redundancy zone.

The Tw-CAD exploitation has revealed a controllability measure threshold . Interval  is a good controllability zone where tests are been generated without problems. Interval of measures  is a bad controllability zone where the tests of some faults will not be found, that will degrade test quality and will increase designing time expenses; here  is a measure maximum.

Observability measure of bit defines, how far is it from circuit outputs, i.e. is it difficult to transport its logic value to outputs:

• the greater measure - the worse observability
• The best measures equal 1 are assigned to output bits
• The measures of other bits are defined as the difference of controllability measures of those bit, that nearest to an output, and estimated one
• Let’s relate the non- observation bits to a redundancy zone and give them a measure that exceeding maximal measure

The Tw-CAD exploitation experience has revealed an observability measure threshold . Interval  is a good observability zone where tests are been generated without problems. Interval of measures  is a bad observability zone, where the tests of some faults will not be found, that will degrade test quality and will increase designing time expenses.

If any bit is included both in a good controllability zone and a good observability zone, its test is calculated quickly and productively. If bit is not included even in one of good zones, it entails increase of time expenses on test generation and therefore its bad quality. General representation of a confident test generation zone is given with a testability zone that is intersection of good controllability and observability zones. Having counted up number of bits included to testability zone it is possible to make representation on problems expected at ATPG in each case:

·       ideal circuit: good controllability, observability and testability zones coincide, a redundancy zone is empty; 100% of bits are in a confident test generation zone, hence, the Hi Fi test will be generated quickly

·       testable circuit: all bits except redundant ones are included in a testability zone; the Hi Fi test will be generated at moderate time expenses

·       good circuit: a good testability zone is comparatively large; the generation time should not be long and the test quality should not be bad

·       bad circuit: the testability zone is comparatively small, the generation time is excessively long, the fault coverage is poor.

The only that two last cases differ is the testability zone size. In both cases decrease of test quality and increase of its generation time is caused by bits not included in the testability zone and also by bits from the redundancy zone.

 

The test quality prediction and the testability improving

The test quality in diagnostics is estimated by the fault coverage, i.e. on ratio of number of checked faults to their general number. In Tw-CAD the optimistic test quality prediction is calculated as the ratio of number of bits in the testability zone to general number of bits without redundant ones. The test quality prediction can be expressed in parts or percents. The controllability and observability measures used in the prediction are counted by expected expenses for test generation. The optimistic measures are based on high efficiency [4] of the ATPG of the Tw-CAD. It is supposed that calculations will pass without in-vain-search, however it is not always right. The prediction can be made more realistic using anticipatory logic verification of the circuit project. During verification the attempt of calculation of home sequence is made for each bit. The realistic prediction of quality P (%) expressed by the formula

,

• where B is a set of bits |B| is number of bits in set B
  all co-factors , , , 1-are binary attributes
• attributes of belonging of bit b to good zones of controllability and  observability
•  is attribute of “verification of bit b is OK”
• R is a united redundancy zone on controllability and observability observability respectively,
•  is attribute of belonging to this zone R
• the product of attributes  corresponds to a testability zone

Except the parameters accounted in the formula, there is a number of difficultly predictable circumstances. For example, undetectable faults cause in-vain-search and degrade the test quality and increase time expenses.

The test quality is predicted upon testability and redundancy zones when the circuit was analyzed. The inverse problem is possible too: changing the testability zone size, it is possible to influence the test quality, this is the essence of the offered approach to DFT process.

Mating of procedures of ATPG and DFT is based on technology DFT&TFD (Design for Test and Test for Design). The circuit processing according to offered technology is presented at a fig. 1. 

                            

	for source circuit at fist pass		for modified circuit at second pass

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

   Fig.1. Offered DFT&TFD technology

 

 

The test quality is improved, when the testability zone extends in process of insertion of additional control points (ACP) and additional observation points (AOP). The bad circuit becomes good and good one becomes testable or even ideal. However the redundancy zone interferes with circuit transition into ideal circuit and achievement of a desirable quality level. Other obstacle is unacceptable large volume of the additional circuitry and third obstacle is presence of mistakes and miscalculations in the project, absence of resets and sets, probably, even not necessary for normal functioning. The bits not past verification are quality increase reserve.

There is an automatic testable recommendation generator (ATRG) in the Tw-CAD. Using ATRG experience, we can show the typical diagram of test quality increase as insertion of additional points, see fig. 2

• where abscissa axis is total amount N of introduced ACP and AOP
• ordinate axis is the test quality prediction P (%)

The diagram looks like “a ladder to success” with varied step height and width. Ladder is leading to high quality test. Estimating efficiency of introduced ACP and AOP, ATRG selects best of them. As approaching 100% the effect of point insertion is decreased (step height) and the point amount increases (step width). It follows from the analysis of „quality ladder“ behavior. Having limited value Р about 100% but Р<100%, it is possible to reduce volume of the additional circuitry essentially. It is important that the designer decide himself, what step of „quality ladder“ (level P) he has a right to rise on, having spent N of additional points; he also decides, how to realize modifications.

 

 

 

 

 

 

 

 

 

 

 

 
Fig. 2 Quality ladder 

 

Aspiring to high quality test the designer realizes the following operations under the verification report and the testability report:

·   Designer revises the circuit project trying to reach the 100% verification ideally

·   Designer eliminates redundancy where possible

·   Designer inserts recommended ACP, i.e. additional sets/resets, multiplexers, virtual JTAG inputs - for controllability at first and observability improvement in consequence

·   Designer inserts recommended AOP, i.e. new outputs including virtual JTAG outputs - for observability improvement only

·   Designer searches for the compromise between desirable test quality and acceptable volume of the additional circuitry trying to reach the quality prediction 100% ideally

 

Practice of Tw-CAD application

Thousands of digital circuits which dimension is from several hundreds to 12 thousands of gates were processed by the Tw-CAD. There are discussed no statistics but typical examples only. The system confidently predicts cases of bad quality and large time expenses on ATPG. It is possible to improve a situation having circuit modified under the recommendations from the ATRG.

The circuit data are shown in the table, where every circuit (frame) is allocated with a horizontal line. There is the name of the initial circuit in the first line of a frame and there are the circuit data with the modifications on ACP/AOP numbers in the second line. The measures of C, O, T, V, P mentioned in the formula and also fault coverage H are specified in the table columns. The reference to the number in the table, for example , consists of symbol of the measure V and the circuit name М29 as an index. The literal part of the circuit name specifies technology of circuit production:

·       P is printed circuits

·       L is the programmed logic integrated circuits (PLD) of firm „Altera”

·        M is gate arrays

 

Circuit	Measure, %						Circuit	Measure, %
	C	O	T	V	P	H		C	O	T	V	P	H
M2	100	100	100	100	100	100	M4 1/1	100 100	97 100	97 100	100	97	98
M8	100	100	100	100	100	99
L2 0/0	100 100	100 100	100 100	77 95	77 95	78 97	M1 2/1	98 100	88 99	86 99	99	86	95
P1 1/0	100 100	94 100	94 100	100	93	93	L24 2/2	100 100	85 99	85 99	98	83	81
M30 3/0	98 100	84 100	82 100	98	81	80	P5 3/2	84 98	92 99	77 97	94	73	82
P2 4/0	100 100	79 100	79 100	100	78	89	P6 5/2	70 99	83 100	59 99	44	26	19
M29 7/0	79 100	59 100	46 100	96	45	60	M21 8/1	88 98	90 99	79 97	93	73	76
M101 25/0	45 100	52 92	25 92	99	25	50	M32 11/5	73 99	88 100	67 99	97	65	79

 

Consider an influence of the various measures on the prediction P and the fault coverage H achieved in ATPG, see above table for numbers:

• the circuit M2 is ideal with 100% testability and 100% verifications - such ones take place rarely
• the circuit M8 is testable judging from measure =100%, but =97% instead of 100% owing to redundancy =3%  - the data on redundancy are not given in the table
• It’s seemed the circuit L2 is to be testable judging from =100%. Prediction  and achieved fault coverage  both are bad due to verification problems (see  =77%). Both parameters have been improved in the revised circuit by elimination of mistakes. In this case the reasons of unsuccessful verification are incorrect control of buses and buffers, long test sequences, absence of resets and sets, design errors - Designer was informed about all details in the verification report
• Bad observability measures for circuits both P1 and P2 are the reasons of decrease of predictions ,  and fault coverage ,
• Both bad controllability  and observability  measures are the reason of bad prediction  and bad fault coverage
• Both bad measures ,  and additionally unsatisfactory verification measure  are the reason of extremely bad measures  and  
• The analysis of the columns C and O for the circuits P1, M30, P2, M29, M101 shows that ACP alone allow frequently to improve both controllability and observability measures
• The given data speak that predictable test quality P and achieved in ATPG fault coverage H are comparable
• Attract for the circuits M21, P6, M101 in addition information on efficiency: 16%, 13%, 2%. With efficiency decrease the predictability estimated as |H - P| becomes worse correspondingly to 7%., 9%, 25%, and the test generation time increases
• worse prediction (see circuits from P1 to M32) - more circuit changes (ACP and AOP) are required
• Dimension of the circuits aggravates problems: see, for example, the circuit M101, it's bad with big dimension. For the circuit M101 redundant chains (duplicated pins, „ground” and „Vcc” chains) really give 17% and it interferes with improvement of measure

 

The bad circuits are paradoxical usually:

·       the greater search expenses - the worse efficiency

·       the greater test generation time - the worse quality

For the good circuits test generation time and high quality of test are predicted:

• for greater test generation time – for better its quality
• time expenses increase practically linearly with increase of circuit dimension

 

Testware designing via Internet

Using allowable in MAX Plus II description of the source circuit (VHDL, AHDL, ORCAD) customer creates his own circuit. Designer uses project-time libraries of ICs and other design modules. MAX Plus II redesigns the customer’s circuit as PLD in terms of PLD base modules (buffers, flip-flops, gates). The library of base modules of MAX Plus II is created in the Tw-CAD too. The Tw-CAD perceives PLD in base modules and requires only the list of modules that formed in rpt-file at this level. This file is a listing of the customer’s circuit compiling in MAX Plus II. Tests of PLDs are synthesized under the description of base modules level in the Tw-CAD. The testing of real circuit is guaranteed. Confidentiality is guaranteed too due to abroad absence of primary project, customer source circuit, time parameters, project-time library.

New library of base modules must be created too for PLDs of other firms like Altera. In case of need it is possible to replenish the library of the Tw-CAD with modules in other circuitry, there is a library of middle scale ICs already. The Tw-CAD generates the test in format of MAX Plus II. The test post processor allows adjusting of the generated test to new formats. It is possible to send the circuit via e-mail zvp@unitel.spb.ru and to receive the designed testware via e-mail too. The software is been developed now to design the testware in virtual laboratory via Internet (see the site http://twcad.ifmo.ru).

The offered testability measure of the digital circuits allows

·       to unite DFT and ATPG

·       to estimate customer’s digital circuits and to classify them

·       to make the reasonable choice of testable modifications to improve testability

·       to predict test quality before and after modifications been made

·       to guide ATPG process

The Tw-CAD automates chores on testware creation, leaving the designer with scope for creative work on the project.