References
under the Tw-CAD Project Period
Note: The main theoretical publications have been translated from "Automatics
& Telemechanics" Journal from
1.Industrial ATPG system, O.F.Nemolochnov, A.E.
Usviatsky, V.F.Zviaguine, V.N. Golynichev, USIM, N5, 1981, p.p.37-42,
"Naukova Dumka", Kiev.
2. Automated test system for faults location -
ASKOPON, V.N. Blochin, L.I. Vorobieva, G.L. Golovanevsky, O.F.Nemolochnov /
USIM, 1981, N2, pp.67-71.
3. The method for synthesis of hazard free
sequencies of logical circuits, V.P.Zviaguine, V.N. Golynichev,
O.F.Nemolochnov./ Automatics and Computer Technics, 1979, N5, pp.33-40,
'Zinatne', Riga.
4. The regular method for synthesis of test
sequencies. Home sequence problem, V.N. Golynichev, V.P.Zviaguine,
O.F.Nemolochnov./ Automatics & Telemechanics, 1981, N9, pp.162-172,
'Nauka', Moscow.
5 The regular method for synthesis of test
sequencies. Hazards and races free checking sequence, V.N. Golynichev,
V.P.Zviaguine, O.F.Nemolochnov / Automatics & Telemechanics, 1984, N1,
pp.125-134.
6. The method for races analise upon cubic
covers of logical circuits, O.F.Nemolochnov, A.E. Usviatsky/ Automatics &
Telemechanics,, 1977, N2, pp.126-135.
7. The Method for synthesis of hazards and
races free checking sequencies for logical circuits with Ì-S-flip-flops,
V.P.Zviaguine, O.F.Nemolochnov., Sloev B.A../ Automatics and Computer Technics,
1983, N4, pp.53-58, 'Zinatne', Riga.
8. Levels identification for logical circuits with
global loops,V.P.Zviaguine, 'Transactions of High Schools, div. of
Instrument building', 1986, N1, pp.33-40.
9. Subsystem of test re-edition, V.P.Zviaguine,
Transactions of High Schools, div. of Instrument building, 1987, N7, pp.29-33.
10. Program realization of the regular method for
synthesis of test sequencies, V.N. Golynichev, V.P.Zviaguine,./
Electronics Modeling, N3, 1987, pp.96-97.
11.Reprezentation of logical elements of digital
circuits for test generation, V.N. Golynichev,/ USIM, 1986, N2, pp.37-40.
.
12. Controlability measures for logical circuits
with global loops, V.P.Zviaguine, A.A. Butylin, High school set of scientific
works "CAD in radioelectronics and computers", V.8, "CAD in
electronics", Vilnus, 1988, pp. 97-109.
13. Verificaction of gate arrays upon prototype,
V.P.Zviaguine, E.D. Shesterkin, Transactions of High Schools, div. of
Instrument building', 1991, v XXXIÓ, N11, pp.38-41.
14. Search reduction rools in the regular method
for synthesis of test sequencies, V.N. Golynichev, V.P.Zviaguine, /USIM,
N2 1990, pp.32-39,"Naukova Dumka", Kiev.
15.Subsystem for estimation of digital circuit
testability V.P.Zviagin A.A.Butylin K.L.Pliusin
16. Design Technology for Digital Circuit Testware
V.P.Zviagin, M.M. Zinatullin, Transactions of High
Schools, div. of Instrument building, 2003, v.46, N1, pp.42-47
Sorry, all above texts are published only in Russian in central
technical journals of the former USSR.