Test for Design (TFD) by the ATPG
Test for Design generated by the Tw-CAD will have fault coverage not more than that predicted.
The unique facility of the Tw-CAD is the ATPG. Test is automatically generated for whole arbitrary circuit ( it contains loops, complex nets, buried flip-flops, etc.) in opposite to the single chip of restricted structure traditionally.
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Test is designed as segmented to number of independent parts (named as "segments") which are not ordered |
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Every segment cosists of well-ordered patterns |
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Every segment is free of hazards and races not only for the good circuit but for the detected faults as well |
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Every segment covers at least one new fault |
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Additional faults are covered symmetrically in some segments |
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Every segment is supplied with found reset or found sequence for initializing |
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Accidentally checked faults are marked in every segment |
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The ATPG uses time-restricted procedure guided by controlability measures. |
We transform test to the needed format (MAX-II Plus, PCAD, DixiCAD, Mr-CAD. etc..). List is to be continued..
We can produce verification test and bus consistency analysis as optional features.
