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Технология проектирования тестового обеспечения DFT & TFD

качество превыше всего

DFT - традиционная аббревиатура для "Design for Test" (тестопригодное проектирование), но нетрадиционный подход к обеспечению тестопригодности

TFD - вместо традиционного для автоматической генерации тестов ATPG, чтоб подчеркнуть двойственность DFT &TFD в разработке тестового обеспечения (TestWare)

Термин "тестовое обеспечение" (TestWare) соединяет все составляющие качественного тестирования, четко разъясняя заказчику, из чего складывается качество теста для его схемы:

·    верифицирован ли проект ?
·    правильно ли работают шины и двунаправленные магистралиcorrectly ?
·    нет ли избыточности, препятствующей достижению высокого качества теста ?
·    тестопригодна ли схема настолько, чтоб автоматически сгенерировать тест ?

To answer the above questions the source circuit is analyzed and the designer receives:

• The report on automatic verification
• The report on a consistency of buses and bidirectional ports
• The report about testability, including
  + the recomendations on where additional control points (ACP) are to be placed as additional inputs for improvement both controlability and observability
  + the recomendations on where additional observation points (AOP) are to be placed as additional outputs for observability improvement only
  + the forecast of test quality for the source circuit and the changed one
  + the diagram of change of fault coverage in process of addition of ACPs and AOPs for planning of the test quality

When designer will realize testable modifications he will receive

• The specified report on automatic verification
• The specified report on testability, including the specified forecast of test quality reachable in the ATPG
• The list of detected, undetected and undetectable faults
• The automatically generated HW test in the ordered format

Essence of technological stages in brief is as following::

• The misunderstanding of the circuit or any decisions are found out beforehand in procedure of generation of the verification test automatically
• Any home sequence is to be generated for each value of every node in verification procedure; each by another from complex to simple nodes are been verified in 0, 1, maybe Z values. It is good, if the sequences exist
• The misses in the control of buses and bidirectional ports is checking by calculation of contra examples pointing out on wrong work. It is good, if they do not exist.
• Testability is measured as the forecast of achievable quality of the test. It is good, if 100 % is reachable
• If the forecast is unfavourable then the automatic generator of testable modifications starts
• The economic modifications making possible automatic generation of the test are recommended to customer
• It is underlined how the quality of the test is been improved in process of modifications been inserted
• Designer under the submitted report and diagram searches for a compromise between desirable quality of the test and necessary changes of his circuit
• Achievable quality of the test is specified and the hardware test for the changed circuit is automatically generated.

 

Analysis of source circuit and forecast of  test quality

• At first model of a circuit is to be constructed to analize structure and to put in good order the bits
• A "bit" is a node, which the logic value is attributed by. A node is an input, flip-flop, logical element or output buffer of the circuit.Controlability and observability measures are calculated  for every bit on a base: more measure - more complexity
• Controlability characterizes complexity of management of bits from input side
• Observability characterizes complexity of supervision of bits from output side
• The measures are determined as optimistic, not taking into account search problem arising during generation of the test
• Testability  is constructed as ratio of number of bits in the area where measures both good to total number of bits. The thresholds of good measures are chosen from of  the Tw-CAD great experience in industry. It meets to the zone of the sure ATPG.

 

Further all about the sample circuit named as "FLEXER"...

..but here may be analyse of your own circuit be placed..

DFT Report - about testability of source circuit FLEXER

Let's construct area of good controlability measures		Brown internal circle - 60 % from total  100 % of bits
Let's construct area of good observability measures		Blue  internal circle  – 50% from total  100% of bits
Let's construct good Testability Zone - common red area where previous measures both good	The optimistic forecast of test quality only 29%	The red area makes 29 % from total 100 % of bits

Estimate and select the best ACPs - Additional Control Points

Let's add ACPs therof  Brown area of good controlability measures is expanded ..		Brown area has been expanded up to 95%
As a consequence dark blue area of good observability measures is expanded too ..		Blue area has been expanded up to 80%
Let's construct advanced testability Zone - common red area where previous two measures both good ..		Red area has been expanded up to 76%
	Predicted quality of the test is   76 % only - leaves to wish best

Estimate and select the best AOPs -  Additional Observation Points

Let's add AOPs, repeatedly having expanded dark blue area of good observability measures  ..		The blue area repeatedly has  been expanded up to 97 %
Let's construct double advanced testability zone - common red area where the advanced controlability and the advanced observability measures both good		Red area has extended up to  92%
	The quality of the test, seems, already quite good ? Let's go next step..

Generation of the verification test for a rating of influence of arising search problems on quality of the future hardware test of sample circuit FLEXER.

Let's generated verification test has reached 90% Optimistic forecast of the test quality was 92%		There is a problem not only in testability of the project.  The circuit needs in additional debugging too.
	Thereof general forecast of the HW test quality is possible to expect at a level 83 %

The given percentages illustrate the fact that generation of the test is a complex problem. The matter is that at apparent propriety of impact percentages the total percentage of test quality frequently turns out unsufficient. And we here show, of what parts it develops. From this analysis also it is possible to conclude that achievement of quality close to 100 % need the exact decision of discussed intermediate tasks. According to offered technology in the Tw-CAD's report  thoroughly both the problems are particularly stated and the decisions for each circuit individually are offered.

The recommendations for testability improvement  and forecast of the test quality

The Tw-CAD simulates sequential points insertion and informs designer about the place and a kind of the offered recommendations for improvement of controlability and observability  not just above diagrams. Offering the recommendations we do not fix a manner to realize suggested circuit modifications. Diagram predicts how does fault coverage is growing as ACPs and AOPs are been placed. Customer has a choice to plan circuit DFT modifications.

More details about all calculated measures are shown in the following table.
______________________________________________
|         | measures     | PROGNOSIS of        |
| # point |  SUM    MAX  |CONTR OBSERV TESTABLE|
|_________|______________|_____________________|
| source  | 368833 11885 |  87.8% 90.2%  78.6% |<==source circuit's measures
|c 1  146 | 315382 11885 |  89.6% 92.1%  81.7% |c<== Control points
|c 2  111 | 267121 11237 |  91.8% 92.9%  84.8% |
|c 3  107 | 216449  8731 |  93.8% 94.5%  88.1% |
|c 4  108 | 190229  8731 |  95.4% 94.5%  89.7% |
|c 5  110 | 167569  6502 |  96.2% 94.5%  90.5% |
|c 6  109 | 145554  6502 |  97.0% 94.5%  91.4% |
|c 7  225 | 124590  6502 |  98.2% 95.1%  93.2% |
|c 8  224 |  98368  6502 |  98.6% 97.3%  95.9% |
|c 9  106 |  81091  4247 |  98.8% 97.3%  96.1% |
|c 10 105 |  65603  2669 |  99.2% 97.3%  96.5% |
|________ |______________|_____________________|
|o 11 186 |  30254   618 |  99.2% 98.0%  97.1% |o<==Observation point,finally
|______________________________________________|
One can point out that it is more important control point insertion (10) rather observation point insertion (1).

Besides this summary diagrams and above measures table we inform designer about following

• about problems during generation of the verification test (absence of resets and home sequences).
• about consistency of buses (opportunity of tri state of the bus and uniqueness of a source in the bus at any moment)
• about consistency of bidirectional ports (any pin should not be both input and output simultaneously)
• about possible additional fault coverage decrease during the ATPG process due to redundancy of the circuit
• about general features of generated hardware test of the changed circuit
• hardware test in the ordered format
• about reached quality of the hardware test
  - including the list of detected faults
  - including the list of undetected faults
  - including the list of undetectable faults

The reached test quality does not exceed this one predicted usually.

More detailed diagram is following for another circuit which has very poor starting prognosis of 65% test quality. To reach good prognosis there are needed more number of addtional control and observation points than above real life sample.

If designer wants he can observ more detailed dagram where three curves presented as measures of

• observability as blue
• controlability as brown
• testability as green

At this diagram prognosis of test quality is been improved as additional points insertion:

• at first position  of the source circuit prognosis is very poor of 65% test quality value
• dotted vertical divider cuts diagram to the left and right sides
• left side where additional control points (1:13) would been inserted - green is equidistant from brown basically but blue grows limply
• right side where additional observation points (14:20) would been inserted - green is equidistant from blue
• blue growth is limply both at left (as consequence of  controlability growth ) and at right (growth of  observability itself)
• green is below both brown and blue - thereof  both these measures are to be good
• ideal of 100% is not reachable at any of three curves for this unit as you see
• near 20-th additional point test quality prognosis is reached 96% but not more for this circuit thereof  satiety for both blue and brown
• even more so verification measure is not present here

Please focus your attention on all-round rectangular components of test quality are discussed with suppoused measures and diagram.