|
To generate test or prior testable modifications, we need your circuit Netlist which is
the only data needed. There are to be described for your circuit: its name, ports, parts
and nodes.
E.g. Altera's products contain complete set of descriptions in the internal
*.rpt file. We do not need timing information, source project library, functional
scheme and so on. Netlist extracted from *.rpt file is the only data
needed.
Remember - we can produce test automatically under
conditions below :
 |
circuit is testable enough for the Tw-CAD
(see later DFT report) |
|
verification is OK |
|
circuit is irredundant |
|
any bus (if any exist) at any moment has
the only source (if any) |
|
it is possible to isolate any pulse
generator (if any exist) |
|
it is possible to isolate any CPU element
(if any exist) |
|
it is possible to address any RAM (if any
exist) from external pins |
Benefit of Verification Test (optional yours or optional
ours)
It is very important for automatic Test Generation System that the verification test is
to be submitted to check model. The ATPG can produce a test of arbitrary circuit but
you want maintain your circuit only. If you have such verification test then let us
send too to verify model.
On the contrary if you want let us do generate the verification test automatically to
send it for your analysing.
We can check consistency of all buses of your circuit as well. At first we find all
sources in each bus. Than we try to search any pair of signals compatible at the same time
in any bus. If it is possible then appropriate bus is inconsistent. We shall send you such
contra examples too.
|
