What are "TestWard" and the Tw-CAD?

"TestWard" (Tw) is a new term meaning complete "Design for Test & Test for Design (DFT&TFD) full-scale service. The Tw-CAD is Soft, library an so on to serve testware. Testware includes tests in appropriate tester or CAD format and DFT modifications of the UUT (unit under test). The Tw-CAD uses low cost IBM-PC to create Testware. Possible applications of the Tw-CAD are ranged from custom Testware design in virtual laboratory via e-mail to using workstation for Testware in the CAD/CAE environment. The Net_List from the output of conventional Netlist editor or Schematic Editor of any CAD is the only data needed to enter the Tw-CAD. Designed test will be transformed to the form which customer needs.

CONTENTS of ARTICLE:

1. The unique facility of the Tw-CAD is the ATPG
2. Since 1979 several thousands of tests have been manufactured by the Tw-CAD users
   Two problems were met in the ATPG..
3. The Tw-CAD transforms DFT idea to the newest DFT&TFD technology with natural roles of Designer and Tw as partners
4. General information about the Tw-CAD
5. Subsystems and Restrictions of the Tw-CAD at IBM-PC
6. Basic original concepts
7. The Tw-CAD provides ATPG for all round testing of LSI, PLD, etc.
8. The Tw-CAD provides automated design for test and test for design facilities
9. We start abroad now ..

The unique facility of the Tw-CAD is the ATPG

Test is automatically generated for whole circuit opposite single chip traditionally. Test is designed as segmented to some independent parts which are unordered. At the same time patterns in any segment are ordered. Every segment is hazard free and races free not only for the good circuit but for the faults checked as well. The Tw-CAD generates the complete set of tests including DC test, AC test, hardware test, verification test.

Furthermore the Tw-CAD offers the newest Design for Test & Test for Design technology (DFT&TFD) instead DFT or ATPG separatly. According to this technology:

1. the fault coverage reachable with the Tw-CAD is predicted
2. the testable modifications are selected for the ATPG to be successful 
3. the high quality test of the modified circuit is generated

This technology is ideal part of the JTAG-style of DFT approach.

Since 1979 several thousands of tests have been manufactured by Tw-users. Two problems were met in the ATPG.

The first trend problem is permanent growth of circuit dimension. This one is solved by Windows generation of the Tw-CAD instead of previous DOS-version. It's well known time spending for ATPG depends on circuit dimension but not in first turn. First time spending depends on circuit testability. Fault coverage would be reached in the ATPG process is predicted by the Tw-CAD before the ATPG. If both circuit verification is OK and prognosis is good then the Tw-CAD guarantees high quality TestWare with moderate CPU time spending. If prognosis is poor then possible testable modifications are simulated automatically by the Tw-CAD. The suboptimal subset of modifications is selected. If designer implements them then high quality ATPG becomes possible too.

The second problem is more confidential one. How do to influence upon designers to insert suggested testable modifications? The recommendatory kind of testable modifications is not effective enough due to indetermination in realization. It is needed more systematical approach is to be involved. The way to solve such kind problems has been supposed by Joint Test Action Group (JTAG). It is the Tw-CAD indeed that provides for software to meet testability and guarantees that all problems of test design should be solved. The Tw-CAD assigns points where extra inputs & outputs are to be placed providing possibility of the ATPG. This happens due to the unique analytic power of the Tw-CAD only.

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The Tw-CAD transforms DFT idea to the newest DFT&TFD technology with natural roles of Designer(D) and the Tw as partners:
- Designer creates circuit project and debugs it with the Tw-CAD by verification ATPG, by simulation of own tests, by testless verification if the prototype exists.
- Tw predicts the ATPG fault coverage upon controlability/observability, generates testable modification needed,
- Designer selects ad-hoc testable modifications or JTAG general style of these ones and uses elements of JTAG architecture.
- Tw generates hardware test automatically (including DC and AC tests of LSIs). The Tw forms TestWard files destined to the Tw/tester or other formats ordered.
- Designer involves balance among reachable fault coverage and silicon overhead needed,
- Tw offers software, tests and service to check boards, LSIs, gate arrays, PLDs, etc.

General information about the Tw-CAD system:
The Tw-CAD is based upon original methods and algorithms.
16 versions of the Tw-CAD were presented: for IBM/370 mainframe at 1979; for IBM/PC DOS at 1989, for WINDOWS 3.1 at 1993, for WINDOWS-NT/95/98/2000 at 1999.
System is written with FORTRAN, C and consists of 80,000 statements (10 Mbytes Software in DOS environment), 3 Mbytes HELP plus Manual.
Software is portable to Work stations.
Thousands of tests for sequential circuits were designed automatically and applied by the Tw-CAD users at 31 enterprises, especially for space applications, e.g. for on board computer of Sovjet space shuttle "BURAN".
User's Manual consists of 200 pages.
Russian and English are enabled to communicate with user.

Subsystems of the Tw-CAD at IBM-PC and its Restrictions are:

The only needed to enter the Tw-CAD is Netlist.

Generated test we can transform to format ordered by user.

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Basic original concepts

The Tw-CAD is being developed in St. Petersburg, Russia.

There are a lot of ICs included into Library of the Tw-CAD. The Tw-CAD provides circuit description both at gate level and at functional tables as well. Adequate checking and analysis of all kinds of complex nets including high impedance nodes, buses, bidirectional pins, resistors, relays. No timing information & delays are needed.

Designed test is segmented to independent sequences containing several patterns usually.

The Tw-CAD provides ATPG for all round testing of LSIs, PLDs:
- verification test,
- parametric test (DC test),
- dynamic test (AC test),
- hardware test.

The Tw-CAD provides automated design facilities as well:
- to carry out ATPG before and after manual test design or instead that,
- to minimize length of segmented test by 20-50%,
- to complement of verification test by hardware test widh estimation of their fault coverage,
- to complement of hardware test by manual test with estimation of their fault coverage,
- to complement of hardware test by manually corrected segments of generated test with estimation of their fault coverage,
- adaptation old segmented test to circuit changed that is to reduce the ATPG time by 2-10 ones,
- to unite test of whole circuit test with that of partial circuit model (the ATPG time spending are to be decreased),
- to estimate fault coverage of test presented,
- to simulate and to calculate responses on stimuli offered,
- to compare response predicted with that simulated,
- to reduce the ATPG time of circuits containing RAMs addressed from input port directly;
- to reduce the ATPG time of circuits containing regular parts;
- to read or to write test with programable interface including tester.

User is interested to improve characteristics of the Tw-CAD in use. Tw-CAD records information about every circuit processed. The Tw-CAD statistics is used by the Tw-CAD's designers to meet that.

The Tw-CAD is developing especially in schematic area. The Tw-CAD designers are interested in information about trends of progress in circuitry.
The Tw-CAD has own adequate facilities for library elements, circuits and tests.
The Tw-CAD may be combined with other CADs which have no ATPG.
The Tw-CAD may be implanted to Workstation CAE to provide for powerful ATPG and to provide DFT analysis and automatic creation of testable modifications.

The Tw-CAD provide interface for other CADs and testers:
- for circuit description at the Tw-CAD INPUT,
- for designed test at the Tw-CAD OUTPUT.

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We start now abroad..
So we are interested contacts yelded us information about Netlist formats and test formats needed for users..

Now Altera devices are served with assertiveness. We work with low level Netlist which consist of FFs & gates. To reach this we read any.rpt file and substitute basic elements from own library covering Altera low level library