Is Your
Circuit Testable Really? We offer you constructive reply!
We fulfil thorough testability analysis of
every bit which is the value "0" or "1" assigned to any
line of your circuit. We calculate two measures per bit (controlability-brown & observability - blue).
We show two histograms of
distribution of
brown &
blue measures upon levels from zero to the worse measure of the maximum
value.
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better==>worse - brown distribution
of controlability - how toil to reach bit from inputs
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worse
<==better - blue distribution of observability - how toil to transport bit onto any output
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dashed lines show the thresholds below which the ATPG is still
possible thereby measures being good
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fault
coverage prediction based upon the testable area surrounded by bright red line where both
controlability & observability measures are good thereof ATPG is possible
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in other
words the
testable area or testability is possibility of ATPG
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If Predicted fault coverage value does not reach of the Permissible quality
threshold then the DFT & TFD for bad circuit will
pass as shown below
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we simulate insertion of extra control pins to select automatically suboptimal set of
control points and to predict new fault coverage
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we select extra observable pins by similar approach
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we send to customer the
recommended testable modifications to improve his circuit
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when
circuit is transformed to the testable one then the TFD passes as below:
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verification test may be
generated automatically (optional)
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bus consistency analysis
may be done automatically (optional)
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high quality test with low level of time consuming should be
generated for the testable project met to our advices
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needed test format is
provided as well
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else the
TFD for good circuit will pass as shown below
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verification test may be
generated automatically (optional)
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bus consistency analysis
may be done (optional)
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high quality test is to be generated with low level of time consuming
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needed test format is
provided as well
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